Clock System

The M31/M33XXA Digitizers uses an internally generated high-quality clock (CLKref) which is phase-locked to the chassis clock. Therefore, this clock is an extremely jitter-cleaned copy of the chassis clock. This implementation achieves a jitter and phase noise above 100 Hz which is independent of the chassis clock, depending on it only for the frequency absolute precision and long term stability. A copy of CLKref is available at the CLK connector (Table 13).

CLKref is used as a reference to generate CLKsys, the high-frequency clock used to sample data.

Advanced: Chassis Clock Replacement for High-Precision Applications: For applications where clock stability and precision is crucial (e.g. GPS, experimental physics, etc.), the user can replace the chassis clock with an external reference. In the case of PXI/PXIe, this is possible via a chassis clock input connector or with a PXI/PXIe timing module. These options are not available in all chassis, please check the corresponding chassis specifications.

CLK Output Options

		Programming Definitions
Disable	The CLK connector is disable	n/a	0 (default)
CLKref Output	A copy of the reference clock is available at the CLK connector	n/a	1

Programming Definitions

Option

Description

Name

Value

Disable

The CLK connector is disable

n/a

0 (default)

CLKref Output

A copy of the reference clock is available at the CLK connector

n/a

Table 13: M31/M33XXA Digitizers output clock configuration

FlexCLK Technology (models with variable sampling rate)

The sampling frequency of the M31/M33XXA Digitizers (CLKsys frequency) can be changed using the advanced clocking system shown in Figure 7.

Figure 7: Functional diagram of the M31/M33XXA Digitizers FlexCLK system

where:

CLKref is the internal reference clock, which is phase-locked to the chassis clock.
CLKsys is the system clock, used to sample data.
CLKsync is an internal clock used for the synchronization features of the M31/M33XXA Digitizers.
PXI CLK10 is the 10 MHz clock of the PXI/PXIe backplane (PXI/PXIe only).

The CLKsys frequency can be changed within the range indicated in the datasheet of the corresponding product (function clockSet- Frequency, Section 2.3.4.17 on page 44). The CLKsync frequency changes with the CLKsys frequency as follows:

The CLKsync frequency is returned by the function clockSetFrequency

CLK Set Frequency Mode

		Programming Definitions
Option	Description	Name	Value
Low Jitter Mode	The clock system is set to achieve the lowest jitter, sacrificing tuning speed	CLK_LOW_JITTER	0
Fast Tuning Mode	The clock system is set to achieve the lowest tuning time, sacrificing jitter performance	CLK_FAST_TUNE	1

Table 14: Clock set frequency mode (function clockSetFrequency